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PM6685
Dual step-down main supply controller with auxilary voltages for notebook system power
Features

6V to 28V input voltage range Fixed 5V - 3.3V output voltages 5V and 3.3V voltage always available to deliver 100mA of peak current 1.237V 1% reference voltage available Lossless current sensing using low side MOSFETs' RDS(on) Negative current limit Soft-start internally fixed at 2ms Soft output discharge Latched OVP and UVP Selectable pulse skipping at light loads Selectable minimum frequency (33kHz) in pulse skip mode 4mW maximum quiescent power Independent power good signals Output voltage ripple compensation
VFQFPN-32 (5mm x 5mm)
Description
PM6685 is a dual step-down controller specifically designed to provide extremely high efficiency conversion with loss-less current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. The pulse skipping technique increases efficiency for very light loads. Moreover, a minimum switching frequency of 33kHz is selectable in order to avoid audio noise issues. The PM6685 provides a selectable switching frequency, allowing either 200kHz/300kHz, 300kHz/400kHz, or 400kHz/500kHz operation of the 5V/3.3V switching sections.
Applications

Notebook computers Tablet PC or slates Mobile system power supply 3 and -4 Cells Li+ battery-powered devices
Table 1.
Device summary
Order code PM6685 PM6685TR Package VFQFPN-32 (5mm x 5mm) VFQFPN-32 (5mm x 5mm) Packaging Tube Tape and Reel
October 2007
Rev 7
1/52
www.st.com 52
Contents
PM6685
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 Constant on time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Soft start and soft end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 30
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PM6685
Contents
8
Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9 10
Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Block diagram
PM6685
1
Block diagram
Figure 1. Functional block diagram
VIN
VCC
REFERENCE GENERATOR
VREF
5V LINEAR REGULATOR
4V
+ -
UVLO
VREF
LDO5 LDO5 ENABLE
PGOOD
- 2.55V +
LDO3
3.3V LINEAR REGULATOR
4.8V
+ UVLO V5SW
OUT3 SKIP FSEL FREQUENCY SELECTOR
- 2.6V +
LDO3 ENABLE VCC
OUT5 BOOT3 BOOT5
HGATE3
LEVEL SHIFTER
3.3V SMPS
5V SMPS CONTROLLER
LEVEL SHIFTER
HGATE5
PHASE3 CSENSE3 COMP3 LDO5 LGATE3 PGOOD3
CONTROLLER
PHASE5 CSENSE5 COMP5 LDO5 LGATE5 PGOOD5 LDO3 ENABLE LDO5 ENABLE EN5
SHDN LDO3 SEL EN3 UVLO LDO3 MODE SELECTOR
STARTUP CONTROLLER TERMIC FAULT
TERMIC CONTROLLER
4/52
PM6685
Pin settings
2
2.1
Pin settings
Connections
Figure 2. Pin connection (top view)
LDO3_SEL
PGOOD3
PGOOD5
COMP5
VREF
OUT5
VCC
32
SGND1 COMP3 FSEL EN3 SHDN PGOOD_LDO3 LDO3 OUT3
31
30
29
28
27
26
25 24 23 22 21 20
SKIP BOOT5 HGATE5 PHASE5 CSENSE5 VIN LDO5 V5SW
1 2 3 4 5 6 7 8 9
BOOT3
EN5
PM6685
19 18 17
10
HGATE3
11
PHASE3
12
CSENSE3
13
LGATE3
14
PGND
15
LGATE5
16
SGND2
5/52
Pin settings
PM6685
2.2
Functions
Table 2.
Pin 1 2 3
Pin functions
Name SGND1 COMP3 FSEL Description Signal ground. Reference for internal logic circuitry. It must be connected to the signal ground plan of the power supply. The signal ground plan and the power ground plan must be connected together in one point near the PGND pin. DC voltage error compensation pin for the 3.3V switching section. Frequency selection pin. It provides a selectable switching frequency, allowing , allowing three different values of switching frequencies for the 5V/3.3V switching sections. 3.3V SMPS enable input. - The 3.3V section is enabled applying a voltage greater than 2.4V to this pin. - The 3.3V section is disabled applying a voltage lower than 0.8V. When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device enters in standby mode. Shutdown control input. - The device switch off if the SHDN voltage is lower than 0.8V (Shutdown mode) - The device switch on if the SHDN voltage is greater than 1.7V. The SHDN pin can be connected to the battery through a voltage divider to program an undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in high impedance (high-Z). Power Good signal for the 3.3V linear regulator. This pin is an open drain output. It is shorted to GND if LDO3_SEL pin is at its low level or if the output voltage on LDO3 pin is lower than 2.6V. 3.3V Linear regulator output. LDO3 can provide 100mA peak current. Output voltage sense for the 3.3V switching section.This pin must be directly connected to the output voltage of the switching section. Bootstrap capacitor connection for the switching 3.3V section. It supplies the high-side gate driver. High-side gate driver output for the 3.3V section. Switch node connection and return path for the high side driver for the 3.3V section.
4
EN3
5
SHDN
6 7 8 9 10 11
PGOOD LDO3 LDO3 OUT3 BOOT3 HGATE3 PHASE3
12 13 14 15 16
Current sense input for the 3.3V section. This pin must be connected through a CSENSE3 resistor to the drain of the synchronous rectifier (RDSON sensing) to set the current limit threshold. LGATE3 PGND LGATE5 SGND2 Low-side gate driver output for the 3.3V section. Power ground. This pin must be connected to the power ground plan of the power supply. Low-side gate driver output for the 5V section. Signal ground for analog circuitry. It must be connected to the signal ground plan of the power supply.
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PM6685 Table 2.
Pin
Pin settings Pin functions (continued)
Name Description Internal 5V regulator bypass connection. - If V5SW is connected to OUT5 (or to an external 5V supply) and V5SW is greater than 4.9V, the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through a 3W (max) switch. - If V5SW is connected to GND, the LDO5 linear regulator is always on. 5V internal regulator output. It can provide up to 100mA peak current. LDO5 pin supplies embedded low side gate drivers and an external load. Device input supply voltage. A bypass filter (4W and 4.7mF) between the battery and this pin is recommended.
17
V5SW
18 19
LDO5 VIN
20
Current sense input for the 5V section. This pin must be connected through a CSENSE5 resistor to the drain of the synchronous rectifier (RDSON sensing) to set the current limit threshold. PHASE5 HGATE5 BOOT5 Switch node connection and return path for the high side driver for the 5V section. High-side gate driver output for the 5V section. Bootstrap capacitor connection for the 5V section. It supplies the high-side gate driver. Pulse skip mode control input. - If the pin is connected to LDO5 the PWM mode is enabled. - If the pin is connected to GND, the pulse skip mode is enabled. - If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is kept higher than 33kHz (No-audible pulse skip mode). 5V SMPS enable input. - The 5V section is enabled applying a voltage greater than 2.4V to this pin. - The 5V section is disabled applying a voltage lower than 0.8V. When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. Power Good signal for the 5V section. This pin is an open drain output. The pin is pulled low if the output is disabled or if it is out of approximately +/10% of its nominal value. Power Good signal for the 3.3V section. This pin is an open drain output. The pin is pulled low if the output is disabled or if it is out of approximately +/10% of its nominal value.
21 22 23
24
SKIP
25
EN5
26
PGOOD5
27
PGOOD3
28
Control pin for the 3.3V internal linear regulator. This pin determines three operative modes for the LDO3. - If LDO3_SEL pin is connected to GND the LDO3 output is always disabled. LDO3SEL - If LDO3_SEL pin is connected to LDO5 the LDO3 internal regulator is always enabled. - If LDO3_SEL pin is connected to VREF and OUT3 is greater than about 3V, the LDO3 regulator shuts down and the LDO3 pin is be directly connected to OUT3 through a 3W (max) switch. OUT5 COMP5 VCC Output voltage sense for the 5V switching section.This pin must be directly connected to the output voltage of the switching section. DC voltage error compensation pin for the 5V switching section.. Device Supply Voltage pin. It supplies the all the internal analog circuitry except the gate drivers (see LDO5). Connect this pin to LDO5.
29 30 31
7/52
Pin settings Table 2.
Pin 32 33
PM6685 Pin functions (continued)
Name VREF EXP PAD Description High accuracy output voltage reference (1.237V). It can deliver 50uA. Bypass to SGND with a 100nF capacitor. Exposed pad.
8/52
PM6685
Electrical data
3
3.1
Electrical data
Maximum rating
Table 3. Absolute maximum ratings
Parameter COMPx,FSEL,LDO3_SEL,VREF,SKIP to SGND1,SGND2 ENx,SHDN,PGOOD_LDO3,OUTx,PGOODx,VCC to SGND1,SGND2 LDO3 to SGND1,SGND2 LGATEx to PGND HGATEx and BOOTx, to PHASEx PHASEx to PGND CSENSEx , to PGND CSENSEx to BOOTx_ V5SW, LDO5 _to PGND VIN to PGND PGND to SGND1,SGND2_ Power Dissipation at Tamb = 25C Maximum withstanding Voltage range test condition: CDF-AEC-Q100-002- "Human Body Model" acceptance criteria: "Normal Performance"
1. LGATEx to PGND up to -1V for t < 40ns 2. PHASE to PGND up to -2.5V for t < 10ns
Value -0.3 to VCC + 0.3 -0.3 to 6 -0.3 to LDO5 + 0.3 -0.3
(1)
Unit V V V V V V V V V V V W V
to LDO5 + 0.3
-0.3 to 6 -0.6 (2) to 36 -0.6 to 42 -6 to 0.3 -0.3 to 6 -0.3 to 36 -0.3 to 0.3 2 VIN pin Other pins 1000 2000
3.2
Thermal data
Table 4.
Symbol RthJA TSTG TJ
Thermal data
Parameter Thermal resistance junction to ambient Storage temperature range Junction operating temperature range Value 35 -40 to 150 -10 to 125 Unit C/W C C
9/52
Electrical characteristics
PM6685
4
Electrical characteristics
VIN = 12V, TA = 0C to 85C, unless otherwise specified
Table 5.
Symbol
Electrical characteristics
Parameter Test condition Min Typ Max Unit
Supply section VIN Vcc Input voltage range IC supply voltage Turn-on voltage threshold VV5SW Turn-off voltage threshold Hysteresis VV5SW Rdson Maximum operating range LDO5 internal bootstrap switch resistance LDO3 internal bootstrap switch resistance Rdson OUT3, OUT5 discharge mode on-resistance OUT3, OUT5_ discharge mode synchronous rectifier turn-on level Pin Ish Isb Operating power consumption VIN shutdown current VIN standby current VOUT5>5.1V,VOUT3>3.34V V5SW to 5V LDO5, LDO3 no load SHDN connected to GND, ENx to GND, V5SW to GND, LDO3_SEL to 5V 14 270 0.2 V5SW > 4.9V VOUT3 = 3.3V 1.8 1.8 16 4.6 20 Vout=Vref, LDO5 in regulation FSEL to GND 5.5 4.5 4.8 4.75 50 5.5 3 3 25 28 5.5 4.9 V V V V mV V
0.35
0.5
V
4 18 380
mW A A
Shutdown section Device on threshold VSHDN Device off threshold 1.2 0.8 1.5 0.85 1.7 0.9 V V
Soft start section Soft start ramp time 2 3.5 ms
10/52
PM6685 Table 5.
Symbol
Electrical characteristics Electrical characteristics (continued)
Parameter Test condition Min Typ Max Unit
Current limit and zero crossing comparator ICSENSE Input bias current limit Comparator offset VCSENSE-VPGND 90 -6 -1 -120 100 110 6 11 A mV mV mV
Zero crossing comparator offset VPGND-VPHASE Fixed negative current limit threshold On time pulse width OUT5=5V FSEL to GND OUT3=3.3V Ton ON-time duration FSEL to VREF FSEL to LDO5 OFF time TOFFMIN Minimum off time OUT5=5V OUT3=3.3V OUT5=5V OUT3=3.3V VPGND-VPHASE
1685 780 1115 585 830 470
1985 920 1315 690 980 555
2285 1060 1515 ns 795 1130 640
400
500
ns
Voltage reference Voltage accuracy VREF Load regulation Undervoltage lockout fault threshold Integrator Normal mode Over voltage clamp COMP Under voltage clamp Line regulation Both SMPS, 6V UVLO, ILDO3=0A VOUT5>5.1V, VOUT3>3.34V 270 3.94 350 4 4.9 5.0 5.1 0.004 400 4.13 V %/V mA V 0.004 %/V Pulse skip mode 60 -150 mV 250 4.2VILDO5 UVLO
11/52
Electrical characteristics Table 5.
Symbol LDO3 linear regulator VLDO3 ILDO3 LDO3 linear output voltage LDO3 current limit 0.5mA UVLO 3.23 130 3.3 165
PM6685
Electrical characteristics (continued)
Parameter Test condition Min Typ Max Unit
3.37 200
V mA
High and low gate drivers HGATEx high state (pullup) HGATE Driver On-resistance HGATEx low state (pulldown) LGATEx high state(pullup) LGATE Driver On-resistance LGATEx low state (pulldown) PGOOD pins UVP/OVP protections OVP UVP Over voltage threshold Under voltage threshold Upper threshold (VFB-VREF) PGOOD3,5 Lower threshold (VFB-VREF) IPGOOD3,5 VPGOOD3,5 PGOOD LDO3 PGOOD leakage current Output low voltage Rising voltage threshold Falling voltage threshold Hysteresis IPGOOD_LDO3 PGOOD leakage current VPGOOD_LDO3 Output low voltage Thermal shutdown TSDN Shutdown temperature 150 C VPGOOD LDO3 forced to 5.5V ISink = 4mA 150 72.1 20 VPGOOD3,5 forced to 5.5V ISink = 4mA 150 77.7 76.6 30 1 250 90 92 94 1 250 81.1 % uA mV % % mV uA mV Both SMPS sections with respect to VREF. 113 66 107 116 70 110 120 72 113 % % % 0.8 1.2 1.6 1.4 2.7 2.1 2.0 3
Power management pins SMPS disabled threshold EN3,5 SMPS enabled threshold
(2) (2)
0.8 V 2.4 0.5
(2)
Low level(2) FSEL Frequency selection range Middle level 1.0 VLDO5-0.8
VLDO5-1.5
V
High level(2)
12/52
PM6685 Table 5.
Symbol LDO3 SEL
Electrical characteristics Electrical characteristics (continued)
Parameter 3.3V linear regulator selection pin Pulse skip mode Test condition Always-off level
(2)
Min
Typ
Max 0.5
Unit
Bootstrap level(2) Always-on level
(2) (2) (2) (2)
1.0 VLDO5-0.8
VLDO5-1.5
0.5 1.0 VLDO5-0.8 1 1 0.1 1 1 A VLDO5-1.5 V
SKIP
PWM mode Frequency clamp mode
VEN3,4= 0 to 5V VSKIP= 0 to 5V Input leakage current VSHDN= 0 to 5V VFSEL= 0 to 5V VLDO3_SEL= 0 to 5V
1. by demoboard test 2. by design
13/52
Typical operating characteristics
PM6685
5
Typical operating characteristics
FSEL = GND (200/300kHz), SKIP = GND (skip mode), LDO3_SEL = VREF, V5SW = OUT5, input voltage VIN = 12V, SHDN, EN3 and EN5 high, no load unless specified. Figure 3. 5V output efficiency vs load current Figure 4. 3.3V output efficiency vs load current
Figure 5.
PWM no load input battery vs Figure 6. input voltage
Skip no load battery current vs input voltage
14/52
PM6685 Figure 7. Standby mode input battery current vs input voltage Figure 8.
Typical operating characteristics Shutdown mode input device current vs input voltage
Figure 9.
5V switching frequency vs load current
Figure 10. 3.3V switching frequency vs load current
Figure 11. LDO5 vs output voltage
Figure 12. LDO3 vs output voltage
15/52
Typical operating characteristics Figure 13. 5V voltage regulation vs load current
PM6685 Figure 14. 3.3V voltage regulation vs load current
Figure 15. Voltage reference vs load current
Figure 16. OUT5, LDO3 and LDO5 Power-Up
Figure 17. 5V PWM load transient
Figure 18. 3.3V PWM load transient
16/52
PM6685 Figure 19. 5V soft start (0.75 load)
Typical operating characteristics Figure 20. 3.3V soft start (0.55 load)
Figure 21. 5V soft end (no load)
Figure 22. 3.3V soft end (no load)
Figure 23. 5V soft end (1 load)
Figure 24. 3.3V soft end (1 load)
17/52
Typical operating characteristics Figure 25. 5V no audible skip mode
PM6685 Figure 26. 3.3V no audible skip mode
18/52
Application schematic
V+ BOOT1
+
V+ BOOT2 31 18 19 SGND VIN LDO5 VCC VIN SGND 9 BOOT3 HGATE3 HGATE5 21 PHASE5 15 20 PGND 17 SGND 29 30 16 SGND V+ V+ 26 27 5 SGND PGOOD5 VREF PGOOD3 FSEL SKIP EN3 EN5 LGATE5 CSENSE5 V5SW OUT5 COMP5 SGND2 PGOOD5 PGOOD3 SHDN PHASE3 LGATE3 CSENSE3 PGND 10 11 13 12 14 PGND PGND SGND
VIN
PGND
PGND 1 5V+ 22
23
BOOT5
1
+
+
3.3V+
1 5V-
1
3.3V-
Figure 27. Simplified application schematic
PM6685
SGND OUT3 COMP3 PGOOD LDO3 LDO3SEL LDO3
1 8 2 6 28 V+ 7
SGND
Application schematic
V+
PGOODLDO3
SGND
+
SGND 25 32 24 4 3
SGND
SGND
PM6685
6
19/52
Device description
PM6685
7
Device description
The PM6685 is a dual step-down controller dedicated to provide logic voltages for notebook computers. It is based on a Constant On Time control architecture. This type of control offers a very fast load transient response with a minimum external component count. A typical application circuit is shown in Figure 27 on page 19. The PM6685 regulates two fixed output voltages: 5V and 3.3V. The switching frequency of the two sections can be adjusted to approximately 200/300kHz, 300/400kHz or 400/500kHz respectively. In order to maximize the efficiency at light load condition, a pulse skipping mode can be selected. The PM6685 includes also two linear regulators (LDO5 and LDO3) that allow the shutdown of the respective switching sections in low consumption status. On the other hand, to maximize the efficiency in higher consumption status, the linear regulators can be turned off and their outputs can be supplied directly from the switching outputs. The PM6685 provides protection versus overvoltage, undervoltage and overtemperature as well as power good signals for monitoring purposes. An external 1.237V reference is available.
7.1
Constant on time PWM control
If the SKIP pin is tied to 5V, the device works in PWM mode. Each power section has an independent on time control.The PM6685 implements a pseudo-fixed switching frequency, Constant On Time (COT) controller as core of the switched mode section. Each power section has an independent COT control. The COT controller is based on a relatively simple algorithm and uses the ripple voltage due to the output capacitor's ESR to trigger the fixed on-time one-shot generator. In this way, the output capacitor's ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator. On-time one-shot duration is directly proportional to the output voltage VOUT, sensed at the OUT5/OUT3 pins, and inversely proportional to the input voltage VIN, sensed at the VIN pin, as follows: Equation 1
TON = K x
VOUT VIN
This leads to a nearly constant switching frequency, regardless of input and output voltages. When the output voltage goes lower than the regulated voltage Vreg, the on-time one shot generator directly drives the high side MOSFET for a fixed on time allowing the inductor current to increase; after the on time, an off time phase, in which the low side MOSFET is turned on, follows. Figure 28 on page 21 shows the inductor current and the output voltage waveforms in PWM mode.
20/52
PM6685 Figure 28. Constant on time PWM control
Inductor current
Device description
Output voltage
Vreg
DC error Ton Toff t
The duty cycle D of the buck converter in steady state is:
Equation 2
D=
VOUT VIN
The PWM control works at a nearly fixed frequency fSW:
Equation 3
fsw
D = = TON
VOUT VIN =1 K ON VOUT K ON x VIN
As mentioned the steady state switching frequency is theoretically independent from battery voltage and from output voltage. Actually the frequency depends on parasitic voltage drops that are present during the charging path (high side switch resistance, inductor resistance (DCR)) and discharging path (low side switch resistance, DCR). As a result the switching frequency increases as a function of the load current. Standard switching frequency values can be selected for both sections by pin FSEL as shown in the following table:
21/52
Device description
PM6685
Table 6.
FSEL
FSEL pin selection
SMPS 5V Frequency KON 4,7us 3us 2.31us SMPS 3.3V Frequency 297,6kHz 400kHz 500kHz KON 3.36us 2.5us 2.0us
SGND VREF LDO5
212kHz 323kHz 432kHz
The values in the table are measured with Vin =12V, operation mode = PWM and Iload = 2A. The other output are unloaded.
7.2
Constant on time architecture
Figure 29 on page 23 shows the simplified block diagram of a Constant On Time controller. A minimum off-time constrain (380ns typ) is introduced to allow inductor valley current sensing on the synchronous switch. A minimum on-time(150ns typ) is also introduced to assure the start-up switching sequence.
PM6685 has a one-shot generator for each power section that turns on the high side MOSFET when the following conditions are satisfied simultaneously: the PWM comparator is high, the synchronous rectifier current is below the current limit threshold, and the minimum off-time has timed out. Once the on-time has timed out, the high side switch is turned off, while the synchronous switch is turned on according to the anti-cross conduction circuitry management. When the negative input voltage at the PWM comparator, which is a scaled-down replica of the output voltage ripple (see the Rfb1/Rfb2 divider in Figure 29), reaches the valley limit (determined by internal reference Vr=0.9V), the low-side MOSFET is turned off according to the anti-cross conduction logic once again, and a new cycle begins.
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PM6685 Figure 29. Constant ON-time block diagram
Device description
Toff-min Toff-
BOOT CSENSE
Positive Current Limit Vr
+ + - PWM
Comparator gm
S R
Ton
Q Q
Level shifter
HS driver
HGATE PHASE
COMP
+ + 0.5V
0.25V
LDO5 LS driver
+
RFb1
Vr RFb2 Zero-cross. Zero-
-
OUT
S R
Q
LGATE PGND
+ -
Comp.
VIN SKIP
LDO5 0.5V
bandgap 1.236V Vr
VREF
+ -
7.3
Output ripple compensation
In a classic Constant On Time control, the system regulates the valley value of the output voltage and not the average value, as shown in Figure 28 on page 21. In this condition, the output voltage ripple is source of a DC static error. To compensate this error, an integrator network can be introduced in the control loop, by connecting the output voltage to the COMP5/COMP3(for the 5V and 3.3V sections respectively) pin through a capacitor CINT as in Figure 30 on page 24.
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Device description Figure 30. Circuitry for output ripple compensation
COMP PIN VOLTAGE V I=gm(V1-Vr) t COMP OUTPUT VOLTAGE CFILT V gm CINT VCINT Vr t RINT L OUT RFb2 V1 + RFb1 PWM Comparator Vr +
PM6685
Vr
ROUT D COUT
The integrator amplifier generates a current, proportional to the DC errors, which decreases the output voltage in order to compensate the total static error, including the voltage drop on PCB traces. In addition, CINT provides an AC path for the output ripple. In steady state, the voltage on COMP5/COMP3 pin is the sum of the reference voltage Vr and the output ripple (see Figure 30). In fact when the voltage on the COMP pin reaches Vr, a fixed Ton begins and the output increases. For example, we consider VOUT=5V with an output ripple of V=50mV. Considering CINT>>CFILT, the CINT DC voltage drop VCINT is about 5V-Vr+25mV=4.125V. CINT ensures an AC path for the output voltage ripple. Then the COMP pin ripple is a replica of the output ripple, with a DC value of Vr+25mV=925mV. For more details about the output ripple compensation network, see the paragraph "Closing the integrator loop" in the Design guidelines.
7.4
Pulse skip mode
If the SKIP pin is tied to ground, the device works in skip mode. At light loads a zero-crossing comparator truncates the low-side switch on-time when the inductor current becomes negative. In this condition the section works in discontinuous conduction mode. The threshold between continuous and discontinuous conduction mode is:
Equation 4
ILOAD(SKIP) =
VIN - VOUT x TON 2xL
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PM6685
Device description
For higher loads the inductor current doesn't cross the zero and the device works in the same way as in PWM mode and the frequency is fixed to the nominal value.
Figure 31. PWM and pulse skip mode inductor current
PWM mode
Inductor current Load current 0 Ton1 Toff Ton1=Ton2 Ton2
Pulse skip mode
Low side on
Toff Low side off
Time
Figure 31 shows inductor current waveforms in PWM and SKIP mode. In order to keep average inductor current equal to load current, in SKIP mode some switching cycles are skipped. When the output ripple reaches the regulated voltage Vreg, a new cycle begins. The off cycle duration and the switching frequency depend on the load condition.
As a result of the control technique, losses are reduced at light loads, improving the system efficiency.
7.5
No-audible skip mode
If SKIP pin is tied to VREF, a no-audible skip mode with a minimum switching frequency of 33kHz is enabled. At light load condition, If there is not a new switching cycle within a 30us(typ.) period, a no-audible skip mode cycle begins.
Figure 32. Frequency clamp skip mode
Inductor current
No-audible skip mode
30us Time
0 Low side
The low side switch is turned on until the output voltage crosses about Vreg+1%. Then the high side MOSFET is turned on for a fixed on time period. Afterwards the low side switch is enabled until the inductor current reaches the zero-crossing threshold. This keeps the switching frequency higher than 33kHz. As a consequence of the control, the regulated voltage can be slightly higher than Vreg (up to 1%).
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Device description
PM6685
If, due to the load, the frequency is higher than 33kHz, the device works like in skip mode. No-audible skip mode reduces audio frequency noise that may occur in pulse skip mode at very light loads, keeping the efficiency higher than in PWM mode.
7.6
Current limit
The current-limit circuit employs a "valley" current-sensing algorithm. During the conduction time of the low side MOSFET the current flowing through it is sensed. The current-sensing element is the low side MOSFET on-resistance(Figure 33)
Figure 33. RDSON sensing technique
HS
HGATE
PHASE
Rcsense
CSENSE
LS RDSon
LGATE
An internal 100A IL current source (ICSENSE) is connected to CSENSE pin and determines a voltage drop on RCSENSE. If the voltage across the sensing element is greater than this voltage drop, the controller doesn't initiate a new cycle. A new cycle starts only when the sensed current goes below the current limit. Since the current limit circuit is a valley current limit, the actual peak current limit is greater than the current limit threshold by an amount equal to the inductor ripple current. Moreover the maximum output current is equal to the valley current limit plus half of the inductor ripple current:
Equation 5
ILOAD (max) = ILvalley +
IL 2
The output current limit depends on the current ripple, as shown in Figure 34 on page 27:
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PM6685 Figure 34. Current waveforms in current limit conditions
Current DC current limit = maximum load
Device description
Maximum load current is influenced by the inductor current ripple
Inductor current
Valley current threshold
Time
Being fixed the valley threshold, the greater the current ripple is, greater the DC output current is The valley current limit can be set with resistor RCSENSE:
Equation 6
RCSENSE =
RDSon x ILvalley ICSENSE
Where ICSENSE = 100uA, RDSon is the drain-source on resistance of the low side switch. Consider the temperature effect and the worst case value in RDSon calculation. The accuracy of the valley current threshold detection depends on the offset of the internal comparator (VOFF) and on the accuracy of the current generator(ICSENSE):
Equation 7
ILvalley ILvalley
=
RCSENSE RSNS ICSENSE VOFF + + x 100 + ICSENSE RSNS RCSENSE x ICSENSE RCSENSE
Where RSNS is the sensing element (RDSon). PM6685 provides also a fixed negative peak current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in PWM mode. This negative current limit threshold is measured between PHASE and SGND pins, comparing the magnitude drop on the PHASE node during the conduction time of the low side MOSFET with an internal fixed voltage of 120mV. If the current is sensed on the low side MOSFET, the negative valley-current limit INEG (if the device works in PWM mode) is given by:
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Device description Equation 8
PM6685
INEG =
120mV RDSon
7.7
Soft start and soft end
Each switching section is enabled separately by asserting high EN5/EN3 pins respectively. In order to realize the soft start, at the startup the overcurrent threshold is set 25% of the nominal value and the undervoltage protection (see related sections) is disabled. The controller starts charging the output capacitor working in current limit. The overcurrent threshold is increased from 25% to 100% of the nominal value with steps of 25% every 700s (typ.). After 2.8ms (typ.) the undervoltage protection is enabled. The soft start time is not programmable. A minimum capacitor CINT is required to ensure a soft start without any overshoot on the output:
Equation 9
CINT
6uA ILvalley 4 I +L 2
x C out
Figure 35. Soft start waveforms
Switching output
Current limit threshold
EN5/EN3
Time
When a switching section is turned off(EN5/EN3 pins low), the controller enters in soft end mode. The output capacitor is discharged through an internal 16 P-MOSFET switch; when the output voltage reaches 0.3V, the low-side MOSFET turns on, keeping the output to ground. The soft end time also depends on load condition.
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PM6685
Device description
7.8
Gate drivers
The integrated high-current drivers allow to use different power MOSFETs. The high side driver MOSFET uses a bootstrap circuit which is indirectly supplied by LDO5 output. The BOOT and PHASE pins work respectively as supply and return rails for the HS driver. The low side driver uses the internal LDO5 output for the supply rail and PGND pin as return rail. An important feature of the gate drivers is the adaptive anti-cross conduction protection, which prevents high side and low side MOSFETs from being on at the same time. When the high side MOSFET is turned off the voltage at the phase node begins to fall. The low side MOSFET is turned on when the voltage at the phase node reaches an internal threshold. When the low side MOSFET is turned off, the high side remains off until the LGATE pin voltage goes approximately under 1V. The power dissipation of the drivers is a function of the total gate charge Qg of the external power MOSFETs and of the switching frequency, as shown in the following equation:
Pdriver = Vdriver x Q g x fsw
Where Vdriver is the 5V driver supply.
7.9
Reference voltage and bandgap
The 1.237V(typ.) internal bandgap voltage is accurate to 1% over the temperature range. It is externally available (VREF pin) and can supply up to 100A and can be used as a voltage threshold for the multifunction pins FSEL, SKIP and LDO3_SEL to select the appropriate working mode. Bypass VREF to ground with a 100nF minimum capacitor. If VREF goes below 0.87V(typ.) , the system detects a fault condition and all the circuitry is turned off. A toggle on the input voltage (power on reset) or a toggle on SHDN pin is necessary to restart the device. An internal divider of the bandgap provides a voltage reference Vr of 0.9V. This voltage is used as reference for the linear and the switching regulators outputs. The overvoltage protection, the undervoltage protection and the power good signals are referred to Vr.
7.10
Internal linear regulators
The PM6685 has two linear regulators providing respectively 5V(LDO5) and 3.3V(LDO3) at 2% accuracy. High side drivers, low side drivers and most of internal circuitry are supplied by LDO5 output through VCC pin (an external RC filter may be applied between LDO5 and VCC). Both linear regulators can provide an average output current of 50mA and a peak output current of 100mA. Bypass both LDO5 and LDO3 outputs with a minimum 1F ceramic capacitor and a 4,7F tantalum capacitor (ESR < 2). If the 5V output goes below 4V, the system detects a fault condition and all the circuitry is turned off. A power on reset or a toggle on SHDN pin is necessary to restart the device.
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Device description
PM6685
V5SW pin allows to keep the 5V linear regulator always active or to enable the internal bootstrap-switch over function: if the 5V switching output is connected to V5SW, when the voltage on V5SW pin is above 4.8V, an internal 3.0 max p-channel MOSFET switch connects V5SW pin to LDO5 pin and simultaneously LDO5 shuts down. This configuration allows to achieve higher efficiency. V5SW can be connected also to an external 5V supply. LDO5 regulator turns off and LDO5 is supplied externally. If V5SW is connected to ground, the internal 5V regulator is always on and supplies LDO5 output.
Table 7.
V5SW GND Switching 5V output External 5V supply
V5SW multifunction pin
Description The 5V linear regulator is always turned on and supplies LDO5 output. The 5V linear regulator is turned off when the voltage on V5SW is above 4.8V and LDO5 output is supplied by the switching 5V output. The 5V linear regulator is turned off when the voltage on V5SW is above 4.8V and LDO5 output is supplied by the external 5V.
The 3.3V linear regulator is supplied by LDO5 output. LDO3_SEL pin allows to keep 3.3V linear regulator always enabled, always disabled or to enable the internal bootstrap-switch over function. According to Table 7:
If LDO3_SEL is connected to VREF pin, when the power good signal of the 3.3V switching output voltage PGOOD3(see related sections) is high, the internal linear regulator is turned off and LDO3 output is connected directly to OUT3 pin through an internal 3 max p-channel MOSFET switch. If LDO3_SEL is connected to 5V, the internal 3.3V regulator is always on and supplies LDO3 output. If LDO3_SEL is connected to ground, the internal 3.3V regulator is always off and LDO3 output is clamped to ground.
LDO3_SEL multifunction pin
Description The 3.3V linear regulator is always turned off. The 3.3V linear regulator is turned off when PGOOD3 is high. LDO3 output is supplied by the switching 3.3V output. The 3.3V linear regulator is always turned on and supplies LDO3 output.

Table 8.
LDO3_SEL GND VREF LDO5
7.11
Power up sequencing and operative modes
Let's consider SHDN, EN5 and EN3 low at the beginning. The battery voltage is applied as input voltage. The device is in shutdown mode. When the SHDN pin voltage is above the shutdown device on threshold(1.5V typ.), the controller begins the power-up sequence. All the latched faults are cleared. LDO5 undervoltage control is blanked for 4 ms and the internal regulator LDO5 turns on. If the LDO5 output is above the UVLO threshold after this time, the device enters in standby mode. The switching outputs are kept to ground by turning on the low side MOSFETs.
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PM6685
Device description
When EN5 and EN3 pins are forced high the switching sections begin their soft start sequence. LDO3 management is independent from the general power up sequence and depends only on LDO3_SEL .
Table 9.
Mode Run
Operatives modes
Conditions SHDN is high EN3/EN5 pins are high by Both EN5/EN3 pins are low and SHDN pin is high SHDN is low Description Switching regulators are enabled; internal linear regulators outputs are enabled. Internal Linear regulators active (LDO5 is always on while LDO3 depends on LDO3_SEL pin). In Standby mode LGATE5/LGATE3 pins are forced high while HGATE5/HGATE3 pins are forced low. All circuits off.
Stand
Shutdown
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Monitoring and protections
PM6685
8
8.1
Monitoring and protections
Power good signals
The PM6685 provides three independent power good signals: one for each switching section(PGOOD5/PGOOD3) and the other for the internal linear regulator LDO3(PGOOD_LDO3). PGOOD5/PGOOD3 signals are low if the output voltage is out of 10% of the designed set point or during the soft-start, the soft end and when the device works in standby and shutdown mode. PGOOD_LDO3 signal is low when the output voltage of LDO3 output is lower than its falling voltage threshold(2.6V typ.). Each power good pin is an open-drain output and can sink current up to 4mA.
8.2
Thermal protection
The PM6685 has a thermal protection to preserve the device from overheating. The thermal shutdown occurs when the die temperature goes above +150C. In this case all internal circuitry is turned off and the power sections are turned off after the discharge mode. A power on reset or a toggle on the SHDN pin is necessary to restart the device.
8.3
Overvoltage protection
When the switching output voltage is about 115% of its nominal value, a latched overvoltage protection occurs. In this case, the synchronous rectifier immediately turns on while the high-side MOSFET turns off. The output capacitor is rapidly discharged and the load is preserved from being damaged. The overvoltge protection is also active during the soft start. Once an overvoltage protection has been detected, a toggle on SHDN, EN3/EN5 pins or a power on reset is necessary to exit from the latched state.
8.4
Undervoltage protection
When the switching output voltage is below 70% of its nominal value, a latched undervoltage protection occurs. In this case the switching section is immediately disabled and both switches are open. The controller enters in soft end mode and the output is eventually kept to ground, turning low side MOSFET on. The undervoltage circuit protection is enabled only at the end of the soft-start. Once an overvoltage protection has been detected, a toggle on SHDN, EN5/EN3 pin or a power on reset is necessary to clear the undervoltage fault and starts with a new soft-start phase.
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PM6685
Monitoring and protections
Table 10.
Mode
Protections and operatives modes
Conditions Description
Overvoltage protection Undervoltage protection Thermal shutdown
LGATE5/LGATE3 pin is forced high, LDO5 remains OUT5/OUT3 > 115% of the active. Exit by a power on reset or toggling SHDN or nominal value EN5/EN3 OUT5/OUT3 < 70% of the nominal value TJ > +150C LGATE5/LGATE3 is forced high after the soft end mode, LDO5 remains active. Exit by a power on reset or toggling SHDN or EN5/EN3 All circuitry off. Exit by a POR on VIN or toggling SHDN.
8.5
Design guidelines
The design of a switching section starts from two parameters:

Input voltage range: in notebook applications it varies from the minimum battery voltage, VINmin to the AC adapter voltage, VINmax. Maximum load current: it is the maximum required output current, ILOAD(max).
8.6
Switching frequency
It's possible to set 3 different working frequency ranges for the two sections: 200kHz/300kHz, 400kHz/500kHz, 600kHz/700kHz with FSEL pin. Switching frequency mainly influences two parameters:

Inductor size: for a given saturation current and RMS current, greater frequency allows to use lower inductor values, which means smaller size. Efficiency: switching losses are proportional to frequency. High frequency generally involves low efficiency.
8.7
Inductor selection
Once that switching frequency is defined, inductor selection depends on the desired inductor ripple current and load transient performance. Low inductance means great ripple current and could generate great output noise. On the other hand, low inductor values involve fast load transient response. A good compromise between the transient response time, the efficiency, the cost and the size is to choose the inductor value in order to maintain the inductor ripple current IL between 20% and 50% of the maximum output current ILOAD(max). The maximum IL occurs at the maximum input voltage. With this considerations, the inductor value can be calculated with the following relationship:
33/52
Monitoring and protections Equation 10
PM6685
L=
VIN - VOUT VOUT x fsw x IL VIN
where fsw is the switching frequency, VIN is the input voltage, VOUT is the output voltage and IL is the selected inductor ripple current. In order to prevent overtemperature working conditions, inductor must be able to provide an RMS current greater than the maximum RMS inductor current ILRMS:
Equation 11
ILRMS = (ILOAD (max))2 +
(IL (max))2 12
Where IL(max) is the maximum ripple current:
Equation 12
IL (max) =
VIN max - VOUT V x OUT fsw x L VIN max
If hard saturation inductors are used, the inductor saturation current should be much greater than the maximum inductor peak current Ipeak:
Equation 13
Ipeak = ILOAD (max) +
IL (max) 2
Using soft saturation inductors it's possible to choose inductors with saturation current limit nearly to Ipeak. Below there is a list of some inductor manufacturers.
Table 11. Inductor manufacturer
Series SER1360 MLC RLF12560 Inductor value (uH) 4 to 8 2.2 to 4.5 2.7 to 10 RMS current (A) 6 to 8.6 13.6 to 8.8 7.5 to 11.5 Saturation current (A) 7 to 12 11.5 to 17 7.5 to 14.4
Manufacturer COILCRAFT COILCRAFT TDK
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PM6685
Monitoring and protections
8.8
Output capacitor
The selection of the output capacitor is based on the ESR value Rout and the voltage rating rather than on the capacitor value Cout. The output capacitor has to satisfy the output voltage ripple requirements. Lower inductor value can reduce the size of the choke but increases the inductor current ripple IL. Since the voltage ripple VRIPPLEout is given by:
Equation 14
VRIPPLEout = R out x IL
A low ESR capacitor is required to reduce the output voltage ripple. Switching sections can work correctly even with 20mV output ripple. However, to reduce jitter noise between the two switching sections it's preferable to work with an output voltage ripple greater than 30mV. If lower output ripple is required, a further compensation network is needed (see Closing the integrator loop paragraph). Finally the output capacitor choice deeply impacts on the load transient response (see Load transient response paragraph). Below there is a list of some capacitor manufacturers.
Table 12. Output capacitor manufacturer
Series POSCAP TPB,TPD SPCAP UD, UE Capacitor value (F) 150 to 330 150 to 220 Rated voltage (V) 4 to 6.3 4 to 6.3 ESR max (m) 35 to 65 9 to 18
Manufacturer SANYO PANASONIC
8.9
Input capacitors selection
In a buck topology converter the current that flows into the input capacitor is a pulsed current with zero average value. The input RMS current of the two switching sections can be roughly estimated as follows:
Equation 15
2 ICinRMS = D1 x I1 x (1 - D1) + D 2 x I2 x (1 - D 2 ) 2
Where D1, D2 are the duty cycles and I1, I2 are the maximum load currents of the two sections. Input capacitor should be chosen with an RMS rated current higher than the maximum RMS current given by both sections.
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Monitoring and protections
PM6685
Tantalum capacitors are good in term of low ESR and small size, but they occasionally can burn out if subjected to very high current during the charge. Ceramic capacitors have usually a higher RMS current rating with smaller size and they remain the best choice. Below there is a list of some ceramic capacitor manufacturers.
Table 13. Input capacitor manufacturer
Series UMK325BJ106KM-T10 GMK325BJ106MN C3225X5R1E106M Capacitor value (F) 10 10 10 Rated voltage (V) 50 35 25
Manufacturer TAYIO YUDEN TAYIO YUDEN TDK
8.10
Power MOSFETs
Logic-level MOSFETs are recommended, since low side and high side gate drivers are powered by LDO5. Their breakdown voltage VBRDSS must be higher than VINmax. In notebook applications, power management efficiency is a high level requirement. The power dissipation on the power switches becomes an important factor in switching selections. Losses of high-side and low-side MOSFETs depend on their working conditions. The power dissipation of the high-side MOSFET is given by:
Equation 16
PDHighSide = Pconduction + Pswitching
Maximum conduction losses are approximately:
Equation 17
Pconduction = RDSon x
VOUT x ILOAD (max)2 VIN min
where RDSon is the drain-source on resistance of the high side MOSFET. Switching losses are approximately:
Equation 18
Pswitching =
VIN x (ILOAD (max) -
IL I ) x t on x fsw VIN x (ILOAD (max) + L ) x t off x fsw 2 2 + 2 2
where ton and toff are the switching times of the turn off and turn off phases of the MOSFET.
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PM6685
Monitoring and protections
As general rule, high side MOSFETs with low gate charge are recommended, in order to minimize driver losses. Below there is a list of possible choices for the high side MOSFET.
Table 14. High side MOSFET manufacturer
Type STS12NH3LL STS17NH3LL Gate charge (nC) 10 18 Rated reverse voltage (V) 30 30
Manufacturer ST ST
The power dissipation of the low side MOSFET is given by:
Equation 19
PDLowSide = Pconduction
Maximum conduction losses occur at the maximum input voltage:
Equation 20
V Pconduction = RDSon x 1 - OUT V IN max
x ILOAD (max)2
Choose a synchronous rectifier with low RDSon. When high side MOSFET turns on, the fast variation of the phase node voltage can bring up even the low side gate through its gatedrain capacitance CRSS, causing cross-conduction problems. Choose a low side MOSFET that minimizes the ratio CRSS/CGS (CGS = CISS - CRSS). Below there is a list of some possible low side MOSFETs.
Table 15. Low side MOSFET manufacturer
Type STS17NF3LL STS25NH3LL RDSon (m) 5.5 3.5
Manufacturer ST ST
C RSS CGS
0.047 0.011
Rated reverse voltage (V) 30 30
Dual n-channel MOSFETs can be used in applications with a maximum output current of about 3 A. Below there is a list of some MOSFET manufacturers.
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Monitoring and protections
PM6685
Table 16.
Dual MOSFET manufacturer
Type STS8DNH3LL STS4DNF60L RDSon (m) 25 65 Gate charge (nC) 10 32 Rated reverse voltage (V) 30 60
Manufacturer ST ST
A rectifier across the low side MOSFET is recommended. The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high-side MOSFET off and the synchronous rectifier on. It can increase the efficiency of the switching section, since it reduces the low side switch losses. A schottky diode is suitable for its low forward voltage drop (0.3V). The diode reverse voltage must be greater than the maximum input voltage VINmax. A minimum recovery reverse charge is preferable. Below there is a list of some schottky diode manufacturers.
Table 17. Schottky diode manufacturer
Series STPS1L30M STPS1L20M Forward voltage (V) 0.34 0.37 Rated reverse voltage (V) 30 20 Reverse current (uA) 0.00039 0.000075
Manufacturer ST ST
8.11
Closing the integrator loop
The design of external feedback network depends on the output voltage ripple. If the ripple is higher than approximately 30mV, the feedback network (Figure 36) is usually enough to keep the loop stable.
Figure 36. Circuitry for output ripple compensation
COMP PIN VOLTAGE V I=gm(V1-Vr) t COMP OUTPUT VOLTAGE CFILT V gm CINT VCINT Vr t RINT L OUT RFb2 V1 + RFb1 PWM Comparator Vr +
Vr
ROUT D COUT
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PM6685
Monitoring and protections
The stability of the system depends firstly on the output capacitor zero frequency. The following condition should be satisfied:
Equation 21
fsw > k x fZout =
k 2 x C out x R out
where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It determinates the minimum integrator capacitor value CINT:
Equation 22
CINT >
gm Vr x fsw VOUT 2 x - fZout k
where gm=50us is the integrator transconductance. In order to ensure stability it must be also verified that:
Equation 23
CINT >
gm Vr x 2 x fZout VOUT
In order to reduce ground noise due to load transient on the other section, it is recommended to add a resistor RINT and a capacitor Cfilt that, together with CINT, realize a low pass filter (see Figure 36). The cutoff frequency fCUT must be much greater (10 or more times) than the switching frequency of the section:
Equation 24
RINT =
1 C x C filt 2 x fCUT x INT CINT + C filt
Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by:
Equation 25
VRIPPLEINT = VRIPPLEout x
CINT = VRIPPLEout x q CINT + C filt
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Monitoring and protections
PM6685
Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple. If the ripple is very small (lower than approximately 30mV), a further compensation network, named virtual ESR network, is needed. This additional part generates a triangular ripple that is added to the ESR output voltage ripple at the input of the integrator network. The complete control schematic is represented in Figure 37.
Figure 37. Virtual ESR network
COMP PIN VOLTAGE Vr t t V1
T NODE VOLTAGE V1 OUTPUT VOLTAGE V
CFILT
COMP CINT
I=gm(V1-Vr)
Vr
t T
PWM Comparator
+ -
R
R1 L C
RINT
gm
+
Vr V1
RFb1
OUT ROUT
RFb2
D
COUT
The T node voltage is the sum of the output voltage and the triangular waveform generated by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent ESR RESR. A good trade-off is to design the network in order to achieve an RESR given by:
Equation 26
RESR =
VRIPPLE - R out IL
where IL is the inductor current ripple and VRIPPLE is the overall ripple of the T node voltage. It should be chosen higher than approximately 30mV. The stability of the system depends firstly on the output capacitor value and on RTOT:
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PM6685 Equation 27
Monitoring and protections
R TOT = RESR + R out
The following condition should be satisfied:
Equation 28
fsw > k x fZ =
k 2 x C out x R TOT
Where k is a free design parameter greater than 3 and determines the minimum integrator capacitor value CINT:
Equation 29
CINT >
gm Vr x f VOUT 2 x sw - fZ k
In order to ensure stability it must be also verified that:
Equation 30
CINT >
gm Vr x 2 x fZout VOUT
C must be selected as shown:
Equation 31
C > 5 x CINT
R must be chosen in order to have enough ripple voltage on integrator input:
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Monitoring and protections Equation 32
PM6685
R=
L RESR x C
R1 can be selected as follows:
Equation 33
1 Rx Cx x f Z R1 = 1 R- C x x fZ
Example: 5V section, fSW=200kHz, L=4.7uH, Cout=100uF ceramic (Rout~0). We design RESR = 30m. We choose CINT=1nF by equations 31, 32 and Cfilt=47pF, RINT=1.8K by eq.26,27. C=6.8nF by Eq.33. Then R=22K (eq.34) and R1=1K (eq.35).
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PM6685
Other parts design
9
Other parts design
VIN filter A VIN pin low pass filter is suggested to reduce switching noise. The low pass filter is shown in the next figure:
Figure 38. VIN pin filter
R
Input voltage
VIN C 1 0 0 pF
Typical components values are: R=3.9 and C=4.7uF.
VCC filter A VCC low pass filter helps to reject switching commutations noise:
Figure 39. Inductor current waveforms
LDO5 R C VCC
Typical components values are: R=47 and C=1uF.
VREF capacitor A 10nF to 100nF ceramic capacitor on VREF pin must be added to ensure noise rejection.
LDO3 and LDO5 output capacitors
Bypass the output of each linear regulator with 1uF ceramic capacitor closer to the LDO pin and a 4.7uF tantalum capacitor (ESR=2). In most applicative conditions a 4.7uF ceramic output capacitor can be enough to ensure stability.
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Other parts design
PM6685
Bootstrap circuit The external bootstrap circuit is represented in the next figure:
Figure 40. Bootstrap circuit
D RBOOT CBOOT
LDO5 BOOT PHASE
L
The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high side MOSFET during turn on phase. A typical value is 100nF. The bootstrap diode D must charge the capacitor during the off time phases. The maximum rated voltage must be higher than VINmax. A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the phase node rises up, working like a gate resistor for the turn on phase of the high side MOSFET.
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PM6685
Design example
10
Design example
The following design example considers an input voltage from 7V to 16V. The two switching outputs must deliver a maximum current of 5A. The selected switching frequencies are 200kHz for the 5V section and 300kHz for the 3.3V section.
10.1
Inductor selection
OUT5: ILOAD= 5A, 60% ripple current.
Equation 34
L=
5V (16V - 5V) 5.7H 200KHz 16V 0.6 5
We choose standard value L = 6 uH IL(max) = 2.86A @VIN =16V ILRMS = 5.07A Ipeak = 5A + 0.95A = 6.43A OUT3: ILOAD = 5A, 50% ripple current.
Equation 35
L=
3.33 (16 - 3.33) 3.52H 300KHz 16V 0.5 5
We choose standard value L=4 uH. IL(max) = 2.2A @VIN =16V ILRMS = 5.04A Ipeak = 5A + 1.1A = 6.1A
10.2
Output capacitor selection
We would like to have an output ripple greater than 35mV. OUT5: POSCAP 6TPB330M OUT3: POSCAP 6TPB330M
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Design example
PM6685
10.3
Power MOSFETs
OUT5: High side: STS12NH3LL Low side: STS12NH3LL OUT3: High side: STS12NH3LL Low side: STS12NH3LL
10.4
Current limit
OUT5:
Equation 36
ILvalley (min) = ILOAD (max) -
IL (min) = 4.22 A 2
Equation 37
RCSENSE
4.22A 16.25m 686 100A
(Let's assume the maximum temperature Tmax = 75C in RDSon calculation) OUT3:
Equation 38
ILvalley (min) = ILOAD (max) -
IL (min) = 4.19A 2
Equation 39
RCSENSE
4.19A 16.25m 681 100A
(Let's assume Tmax = 75C in RDSon calculation)
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PM6685
Design example
10.5
Input capacitor
Maximum input capacitor RMS current is about 3.4A. Then ICinRMS > 3.4A We put three 10uF ceramic capacitors with Irms = 1.5A.
10.6
Synchronous rectifier
OUT5: Schottky diode STPS1L30M OUT3: Schottky diode STPS1L30M
10.7
Integrator loop
(Refer to Figure 30 on page 24) OUT5: The ripple is greater than 30mV, then the virtual ESR network is not required. CINT =1nF; Cfilt = 47pF; RINT = 1K OUT3: The ripple is greater than 30mV, then the virtual ESR network is not required. CINT =1nF; Cfilt = 47pF; RINT = 1K
10.8
Layout guidelines
The layout is very important in terms of efficiency, stability and noise of the system. It is possible to refer to the PM6685 demoboard for a complete layout example. For good PC board layout follows these guidelines:
Place on the top side all the power components (inductors, input and output capacitors, MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve a layer to PGND plan. The PGND plan is the same for both the switching sections. AC current paths layout is very critical (see Figure 41 on page 48). The first priority is to minimize their length. Trace the LS MOSFET connection to PGND plan as short as possible. Place the synchronous diode D near the LS MOSFET. Connect the LS MOSFET drain to the switching node with a short trace. Place input capacitors near HS MOSFET drain. It is recommended to use the same input voltage plan for both the switching sections, in order to put together all input capacitors. Place all the sensitive analog signals (feedbacks, voltage reference, current sense paths) on the bottom side of the board or in an inner layer. Isolate them from the power top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in one point (a multiple vias connection is preferable to a 0 ohm resistor connection) near the PGND device pin. Place the device on the top or on the bottom size and connect the exposed pad and the SGND pins to the SGND plan (see Figure 41 on page 48).
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Design example Figure 41. Current paths, ground connection and driver traces layout
PM6685
As general rule, make the high side and low side drivers traces wide and short. The high side driver is powered by the bootstrap circuit. It's very important to place capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for example on the layer opposite to the device). Route HGATE and PHASE traces as near as possible in order to minimize the area between them. The Low side gate driver is powered by the 5V linear regulator output. Placing PGND and LGATE pins near the low side MOSFETs reduces the length of the traces and the crosstalk noise between the two sections. The linear regulator outputs are referred to SGND as long as the reference voltage Vref. Place their output filtering capacitors as near as possible to the device. Place input filtering capacitors near VCC and VIN pins. It would be better if the feedback networks connected to COMP and OUT pins are "referred" to SGND in the same point as reference voltage Vref. To avoid capacitive coupling place these traces as far as possible from the gate drivers and phase (switching) paths. Place the current sense traces on the bottom side. Use a dedicated connection between the switching node and the current limit resistor RCSENSE.

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PM6685
Package mechanical data
11
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 18. VFQFPN 5x5x1.0 32L Pitch 0.50
Databook (mm) Dim. Min A A1 A3 b D D2 E E2 e L ddd 0.3 4.85 0.18 4.85 0.8 0 Typ 0.9 0.02 0.2 0.25 5 See exposed pad variations 5 See exposed pad variations 0.5 0.4 0.5 0.05
(2) (2)
Max 1 0.05
0.3 5.15
5.15
Table 19.
Exposed pad variations
(1)(2)D2
E2 Max 3.20 Min 2.90 Typ 3.10 Max 3.20
Min 2.90
Typ 3.10
1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. Very thin: A = 1.00mm Max. 2. Dimensions D2 & E2 are not in accordance with JEDEC.
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Package mechanical data Figure 42. Package dimensions
PM6685
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PM6685
Revision history
12
Revision history
Table 20.
Date 17-Jan-2006 21-Apr-2006 03-May-2006 29-Jun-2006 11-Sep-2006 24-Oct-2006 18-Oct-2007
*
Document revision history
Revision 1 2 3 4 5 6 7 Initial release Few updates Graphical updates Mechanical data updated Changes electrical characteristics, added COMP value skip mode, pin out updated Order code table updated Updated: Current sensing option and absolute maximum ratings Table 3 on page 9. Changes
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PM6685
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